The present disclosure relates generally to semiconductor devices, and more particularly to semiconductor memory devices. Still more particularly, the present disclosure relates to the circuit and method that reduce power consumption of a semiconductor memory device. This modified refresh circuit and method would reduce the device power consumption, thereby improving both efficiency and stability in semiconductor memory devices.
The invention relates to a circuit for controlling information refreshing operations of the memory blocks in a semiconductor memory device, such as a dynamic random access memory (DRAM) device, and to a corresponding method in which a periodic sequence of control signals trigger the information refreshing operation of the DRAM semiconductor device memory blocks.
In DRAMs, it is necessary for the information stored in the memory cells to be periodically refreshed, since the memory cells can retain the information stored in them for only a limited time. Typically, DRAM memory cells use capacitors to store information. Since these capacitors discharge themselves after a specific time as a result of unavoidable internal quiescent currents, the stored charges of the capacitors have to be regularly renewed. The period of time in which the memory cells hold their stored charge is known as its data retention time. The memory cells are therefore recharged at fixed predetermined time intervals, so-called refresh cycles. The pulse for recharging, the so-called refresh pulse, can be generated internally within the module or else externally. In modern DRAMs, refresh cycles of at least 4096 refreshing operations per 64 ms (refresh rate 4K/64 ms) are customary.
The refresh cycle for the DRAM, i.e. the interval between the individual refresh pulses, must be chosen such that even the memory cell with the shortest retention time, which specifies how long the memory content can be retained in the associated cell, is refreshed again before information is permanently lost.
The conventional refresh method for DRAMs perform simultaneous refreshing operations on all memory blocks of the DRAM. This results in a high peak instantaneous current spike within the DRAM device. The current spike generates additional internal noise that can affect circuit operation and cause larger supply voltage fluctuations. In addition, since supply voltage power regulators must be designed to handle this peak current requirement, the overall memory design becomes not only less efficient but also more space-consuming.
Desirable in the art of semiconductor memory device designs are additional designs that may reduce the peak current during memory refresh while improving read/write performance and reducing power consumption.